Search - verilog fifo

[Embeded-SCM Develop] fifo_datapath

Description:
Platform: | Size: 2048 | Author: | Hits:

[Other] FIFO_Memory

Description: VHDL设计——FIFO存储器设计-VHDL design-- FIFO design
Platform: | Size: 7168 | Author: 钱伟康 | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
Platform: | Size: 69632 | Author: 张勇奇 | Hits:

[VHDL-FPGA-Verilog] FIFO_Syn

Description:
Platform: | Size: 25600 | Author: shenyunfei | Hits:

[File Format] good20FIFO1_1156903973

Description: 设计FIFO,使用VERILOG的一篇文章-Design of FIFO, the use of Verilog in an article
Platform: | Size: 119808 | Author: 丁过州 | Hits:

[Other Embeded program] USB2.0_Slave_FIFO_ASync

Description: This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
Platform: | Size: 123904 | Author: MyName | Hits:

[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog

Description: Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
Platform: | Size: 16384 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] afifo

Description:
Platform: | Size: 2048 | Author: dq | Hits:

[VHDL-FPGA-Verilog] generic_fifos.tar

Description: Generic FIFO, writen in verilog hdl
Platform: | Size: 12288 | Author: marco | Hits:

[OS Develop] dfifo

Description: verilog，异步一进一出的例子，空满的标志。-verilog, into an asynchronous one example, air-filled logo.
Platform: | Size: 2048 | Author: 陈虎 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

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[Embeded-SCM Develop] fifo_datapath

[Other] FIFO_Memory

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

[VHDL-FPGA-Verilog] xapp935

[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

[VHDL-FPGA-Verilog] FIFO_Syn

[File Format] good20FIFO1_1156903973

[Other Embeded program] USB2.0_Slave_FIFO_ASync

[VHDL-FPGA-Verilog] Synthesizable_FIFO_verilog

[VHDL-FPGA-Verilog] afifo

[VHDL-FPGA-Verilog] generic_fifos.tar

[OS Develop] dfifo

[VHDL-FPGA-Verilog] 16550

[VHDL-FPGA-Verilog] zzmodelsim

[SCM] IA4420FIFO(C51)

[Other Embeded program] 416fifosource

[VHDL-FPGA-Verilog] asynchoronization_FIFO_design

[VHDL-FPGA-Verilog] asyn_FIFOrealizedbyVerilogHDL

[VHDL-FPGA-Verilog] hdl

[VHDL-FPGA-Verilog] asynch_fifo

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